Simulator minimum time step to ensure convergence. The following list of parameters is used in Microwind2 to configure the simulation. A-xxx: Illustration of the use of LOWK, HIGHK dielectric constants (left figure) or detailed permittivity for each layer (right figure) Details are provided in the table below.įig. Some options are built in Microwind to enable specific features of ultra deep submicron technology. Resistance per square for metal 2 (up to 6) Resistance per square for unsalicide polysilicon Upper SiO2 oxide on the top of the last metalįinal oxide on the top of the passivation, Shallow trench isolation used to separate the Good ground reference underneath the active Vertical crosstalk capacitance refer to interlayer coupling capacitance, while lateral crosstalk capacitance refer to adjacent interconnects.įigure A-2: Description of the 2D aspect of the CMOS technologyīuried layer made of P++ used to create a The name corresponds to the code name used in CMOS012.RUL (CMOS 0.12µm). The list of capacitance handled by MICROWIND2 is given below. Diffused layers generate junction capacitors (N+/P-, P+/N). Basically all layers generate parasitic capacitors. The unit is the aF/µm 2 (atto = 10 -18 ). In the case of complex circuits, MICROWIND2 may skip this cleaning step as it required a significant amount of computational time.Įach deposited layer is separated from the substrate by a SiO2 oxide and generated by a parasitic capacitor. Mainly, redundant boxes are removed, overlapping boxes are transformed into non-overlapping boxes. The first step consists in cleaning the layout. Extract coupling capacitance between nets - Extract net resistanceįigure A-xxx: Extraction of the electrical circuit from layout To select a new foundry, click on File -> Select Foundry and choose the appropriate technology in the list. The default technology corresponds to a generic 6-metal 0.12µm CMOS process.
The process parameters are stored in files with the appendix '.RUL'. The software can handle various technologies. Table 1-xxx: correspondence between technology and the value of lambda in µm Table A-xxx gives the correspondence between lambda and micron for all CMOS technologies available in the companion CD-ROM. The value of lambda is half the minimum polysilicon gate length.
Consequently, the same layout may be simulated in any CMOS technology.
The Microwind software works is based on a lambda grid, not on a micro grid. All that rules, as well as process parameters and analog simulation parameters are detailed here. You will find all the design rule values common to all CMOS processes. This section gives information about the design rules used by Microwind2.
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